1. Field of the Invention
The present invention relates to a potential generating circuit, and particularly to a potential generating circuit charging and discharging an output node in order that a potential of the output node becomes a potential corresponding to a reference potential.
2. Description of the Background Art
With the purpose to reduce power consumption, there has been heretofore provided an internal power supply potential generating circuit for generating an internal power supply potential VO lower than an external power supply potential VCC0 in a semiconductor integrated circuit device.
FIG. 21 is a circuit diagram showing a configuration of such an internal power supply potential generating circuit. In FIG. 21, the internal power supply potential generating circuit includes: an operational amplifier 151; P-channel MOS transistors 152 to 154; and N-channel MOS transistors 155 to 157. Operational amplifier 151 constitutes a voltage follower and outputs a current so as to cause a potential VDDS at a node N151 to coincide with a reference potential VR0. MOS transistors 152, 155, 153 and 156 are connected in series between node N151 and a line at ground potential GND. MOS transistors 157 and 154 are connected in series between a line at external power supply potential VCC0 and the line at ground potential GND. The gates of N-channel MOS transistors 155 and 157 are both connected to the drain of N-channel MOS transistor 155, and the gates of P-channel MOS transistors 153 and 154 are both connected to the drain of P-channel MOS transistor 153. The gates of MOS transistors 152 and 156 are both connected to an output node N157 between MOS transistors 157 and 154. A potential appearing at node N157 is internal power supply potential VO.
Transistor parameters of MOS transistors 152, 155, 153 and 156 are set in order that a potential VC at a node N155 between MOS transistors 155 and 153 is VDDS/2=VR0/2 when internal power supply potential VO is VDDS/2=VR0/2. Furthermore, not only is a threshold voltage of N-channel MOS transistor 157 set to a value higher than that of N-channel MOS transistor 155, but a threshold voltage of P-channel MOS transistor 154 is also set to a value higher than that of P-channel MOS transistor 153 in order that no through current flows into the line at ground potential GND from the line at external power supply potential VCC0 through MOS transistors 157 and 154. With such setting, MOS transistors 157 and 154 are both non-conductive when output potential VO resides in a dead band E1 between a lower limit value VL=VR0/2xe2x88x92xcex94V1 and an upper limit value VH=VR0/2+xcex94V2.
FIG. 22 is a graph showing an operation of the internal power supply potential generating circuit shown in FIG. 21. In FIG. 22, a straight line E in FIG. 22 shows a relationship between output potential VO and a drive current I of the internal power supply potential generating circuit. MOS transistors 157 and 154 becomes non-conductive to cause drive current I to be zero when output potential VO resides in dead band E1. With internal power supply potential VO higher than upper limit VH, not only a resistance value of P-channel MOS transistor 152 becomes higher, but a resistance value of N-channel MOS transistor 156 also becomes lower to lower gate potentials of MOS transistors 157 and 154, to cause P-channel MOS transistor 154 to be conductive, to thereby cause a discharge current to flow and to lower internal power supply potential VO. With internal power supply potential VO lower than lower limit value VL, not only a resistance value of P-channel MOS transistor 152 become lower, but a resistance value of N-channel MOS transistor 96 also becomes higher, to raise gate potentials of MOS transistors 157 and 154, to cause N-channel MOS transistor 157 to be conductive, to thereby cause a charge current flow and to raise internal power supply potential VO. Therefore, internal power supply potential VO is held at a potential between lower limit value VL and upper limit value VH.
In such an internal power supply potential generating circuit, a necessity arises for setting a source-to-drain voltage Vsdp of P-channel MOS transistor 152, a threshold voltage Vthn of N-channel MOS transistor 155, a threshold voltage Vthp of P-channel MOS transistor 153 and a drain-to-source voltage Vdsn of N-channel MOS transistor 156 in order that VC=VDDS/2=VR0/2 when VO=VC.
With lower VDDS, miniaturized layout, constraint from other circuits, fluctuations in fabrication parameters and others, more of difficulty has become a reality in fabrication of MOS transistors in matching Vsdp, Vthn, Vthp and Vdsn with design values. A result ends up with generation of an error voltage xcex94V between internal power supply potential VO and a target potential VR0/2 as shown in FIG. 23 without matching Vsdp, Vthn, Vthp and Vdsn with design values.
In a conventional internal power supply potential generating circuit, not only were threshold voltages of N-channel MOS transistors 155 and 157 adjusted, but threshold voltages of P-channel MOS transistors 153 and 154 were also adjusted to thereby set a width of dead band E1, whereas control of a width of dead band E1 has become harder by a tendency toward lower VDDS and other reasons.
It is, therefore, a main object of the present invention to provide a potential generating circuit capable of correctly controlling a potential at an output node.
It is another object of the present invention to provide a potential generating circuit capable of correctly controlling a dead band width.
A potential generating circuit according to the present invention, as described above, includes: a first transistor of a first conductive type, a first electrode of which is connected to a line at a first power supply potential, and a second electrode of which is connected to a output node; a second transistor of a second conductive type, a first electrode of which is connected to a line at a second power supply potential, and a second electrode of which is connected to the output node; a control potential generating circuit; a monitor potential generating circuit; and a current supply circuit. The control potential generating circuit includes: a third transistor of the second conductive type, a first electrode of which is connected to a first node, an input electrode of which is connected to the output node, and a second electrode of which is connected to an input electrode of the first transistor; a fourth transistor of the first conductive type, a first electrode of which is connected to the line at the second power supply potential, an input electrode of which is connected to the output node, and a second electrode of which is connected to an input electrode of the second transistor; and first and second diode elements connected in series between the second electrodes of the third and fourth transistors, wherein the first and second transistors are controlled in order that a potential at the output node coincides with a potential at a second node between the first and second diode elements. The monitor potential generating circuit includes: a fifth transistor of the second conductive type, a first electrode of which is connected to the first node and an input electrode of which is connected to a third node; a sixth transistor of the first conductive type, a first electrode of which is connected to the line at the second power supply potential, and an input electrode of which is connected to the third node; a third diode element connected between a second electrode of the fifth transistor and the third node; and a fourth diode element connected between the third node and a second electrode of the sixth transistor, wherein a monitor potential is outputted from the third node. The current supply circuit supplies a current to the first node in order that the monitor potential coincides with the reference potential. Therefore, when the monitor potential coincides with the reference potential, a potential at the second node takes the reference potential and a potential at the output node also further takes the reference potential. Accordingly, a potential at the output node can be caused to correctly coincide with the reference potential.
In another potential generating circuit according to the present invention, there are provided: a first comparison circuit; a second comparison circuit; and a drive circuit. The first comparison circuit includes: first and second transistors, input electrodes of which receive a reference potential and a potential at an output node, respectively, and outputs a first signal at a level corresponding to a potential difference between the potential at the output node and a lower limit potential lower than the reference potential by a first offset voltage. The second comparison circuit includes: third and fourth transistors, input electrodes of which receive the reference potential and the potential at the output node, respectively, and outputs a second signal at a level corresponding to a potential difference between the potential at the output node and an upper limit potential higher than the reference potential by a second offset voltage. The drive circuit operates in response to the first and second signals from the first and second comparison circuits, causing a current to flow into the output node when the potential at the output node is lower than the lower limit potential, while when the potential at the output node is higher than the lower limit potential, causing a current to flow out from the output node. Therefore, by setting a first offset voltage of the first comparison circuit, a lower limit potential can be set, and by setting a second offset voltage of the second comparison circuit, an upper limit potential can be set; and a dead band arises between the lower limit potential and the upper limit potential, thereby enabling setting of a width of the dead band with good precision.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.